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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128 Segment LCD Drivers
CMOS
The MC14LC5003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The two devices are functionally the same except for their data input protocols. The MC14LC5003 uses a serial interface data input protocol. The device may be interfaced to the MC68HCXX product families using a minimal amount of software (see example). The MC14LC5004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eight-bit byte is received. MC14LC5004 also has a "read mode", whereby data sent to the device may be retrieved via the IIC bus. The MC14LC5003/MC14LC5004 drives the liquid-crystal displays in a multiplexed-by-four configuration. The device accepts data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. Devices are independently addressable via a two-wire (or three-wire) communication link which can be common with other peripheral devices. The MC14LC5003/MC14LC5004 are low cost version of MC145003 and MC145004 without cascading function. * * * * * * * Drives 128 Segments Per Package May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom Quiescent Supply Current: 30 A @ 2.7 V VDD Operating Voltage Range: 2.7 to 5.5 V Operating Temperature Range: - 40 to 85C Separate Access to LCD Drive Section's Supply Voltage to Allow for Temperature Compensation See Application Notes AN1066 and AN442
MC14LC5003 MC14LC5004
QFP FU SUFFIX CASE 848B
52 1
ORDERING INFORMATION
MC14LC5003FU MC14LC5004FU MCC14LC5003 MCC14LC5004 QFP QFP BARE DIE BARE DIE
PIN ASSIGNMENT
NC OSC1 OSC2 VDD FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 BP1 BP2 BP3 BP4 A0 A1 A2 ENB NC Din DCLK NC FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10
52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 NC FP19 FP18 FP17 FP16 FP15 VLCD VSS FP14 FP13 FP12 FP11 NC
BLOCK DIAGRAM
VLCD OSC1 OSC2 BP1-BP4 FP1-FP32
NC=NO CONNECTION
OSCILLATOR DRIVERS DRIVERS
FRAME SYNC GENERATOR POR DATA AND ADDRESS DCLK Din A0 A1 A2 ENB CONTROL AND TIMING
LCD VOLTAGE WAVEFORM AND TIMING GENERATOR
128 - 32 MULTIPLEX
128-BIT LATCH
128-BIT SHIFT REGISTER
REV 2 10/96
MOTOROLA
MC14LC5003 * MC14LC5004 3-3
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin Vin osc Iin TA Tstg Parameter DC Supply Voltage Input Voltage, Din, and Data Clock Input Voltage, OSCin of Master DC Input Current, per Pin Operating Temperature Range Storage Temperature Range Value - 0.5 to + 6.5 - 0.5 to 15 - 0.5 to VDD + 0.5 10 - 40 to + 85 - 65 to + 150 Unit V V V mA C C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section. ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA= 25C) Characteristic Output Drive Current -- Frontplanes VO = 0.15 V VO = 2.65 V VO = 1.72 V VO = 1.08 V VO = 0.15 V VO = 5.35 V VO = 3.52 V VO = 1.98 V Supply Standby Currents (No Clock) IDD = Standby @ Iout = 0 A ILCD = Standby @ Iout = 0 A IDD = Standby @ Iout = 0 A ILCD = Standby @ Iout = 0 A Supply Currents (fOSC) = 110 kHz IDD = Quiescent @ Iout = 0 A, no loading IDD = Quiescent @ loading = 270pF IDD = Quiescent @ Iout = 0 A, no loading IDD = Quiescent @ loading = 270pF ILCD = Quiescent @ Iout = 0 A, no loading ILCD = Quiescent @ Iout = 0 A, no loading Input Current Input Capacitance IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IDDS ILCDS IDDS ILCDS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 260 260 -240 -240 -40 -- 40 -- 600 600 -520 -520 -35 -- 55 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1.5 -- 2 -- -- -- -- -- -1.5 -- 1 A 2.7 -- 5.5 -- -- 2.7 -- 5.5 -- -- -- -- -- -- -- -- 30 800 50 1500 A IDDQ IDDQ IDDQ IDDQ ILCDQ ILCDQ Iin Cin 2.7 2.7 5.5 5.5 -- -- -- -- -- -- -- -- 2.7 5.5 -- -- -- -- -- -- -- -- -0.1 -- 30 -- 170 -- -- -- -- -- -- 70 -- 400 40 70 0.1 7.5 A pF (continued) Symbol VDD V VLCD V Min Typical Max Unit A
MC14LC5003 * MC14LC5004 3-4
MOTOROLA
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Frequencies OSC2 Frequency @ R1; R1 = 200 k BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 k Average DC Offset Voltage (BP Relative to FP) Input Voltage "0" Level fOSC2 fBP fOSC2 VOO VIL VIL VIH VIH IBH* IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL tw tr, tf tsu th th trec tw tsu 5 5 5 5 2.8 5.5 2.8 5.5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 5 5 2.8 5 5 5 5 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 100 100 23 -50 -- -- 2 3.85 -240 -240 260 260 40 -- -40 -- -520 -520 600 600 55 -- -35 -- 50 100 -- -- 0 0 30 60 10 20 10 20 50 100 10 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 150 150 33 +50 0.85 1.65 -- -- -- -- -- -- -- 2 -- -1 -- -- -- -- -- 1 -- -1 -- -- 20 120 -- -- -- -- -- -- -- -- -- -- -- -- ns s ns ns ns ns ns ns A kHz Hz kHz mV V Symbol VDD V VLCD V Min Typical Max Unit
"1" Level
Output Drive Current -- Backplanes VO = 2.65 V VO = 0.15 V VO = 1.08V VO = 1.72 V VO = 5.35 V VO = 0.15 V VO = 1.98 V VO = 3.52 V Pulse Width, Data Clock DCLK Rise/Fall Time Setup Time, Din to DCLK Hold Time, Din to DCLK DCLK Low to ENB High ENB High to DCLK High ENB High Pulse Width ENB Low to DCLK High (Figure 1) (Figure 1) (Figure 2) (Figure 2) (Figure 3) (Figure 3) (Figure 3) (Figure 3)
NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change.
MOTOROLA
MC14LC5003 * MC14LC5004 3-5
SWITCHING WAVEFORMS
VALID tf 90% CLK 50% 10% tw tw tr VDD GND CLK Din 50% tsu th VDD 50% GND VDD GND
Figure 1.
tw ENB 50% tsu CLK 50% FIRST CLK th trec LAST CLK tw VDD GND VDD GND
Figure 2.
Figure 3.
MC14LC5003 * MC14LC5004 3-6
MOTOROLA
FUNCTIONAL DESCRIPTION
The MC14LC5003/MC14LC5004 has essentially two sections which operate asynchronously from each other; the data input and storage section and the LCD drive section. The LCD drive and timing is derived from the oscillator, while the data input and storage is controlled by the Data In (Din), Data Clock (DCLK), Address (A0, A1, A2), and Enable (ENB) pins. Data is shifted serially into the 128-bit shift register and arranged into four consecutive blocks of 32 parallel data bits. A time-multiplex of the four backplane drivers is made (each backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the corresponding block of 32 bits is made available at the frontplane drivers. A high input to a plane driver turns the driver on, and a low input turns the driver off. Figure 4 shows the sequence of backplanes. Figure 5 shows the possible configurations of the frontplanes relative to the backplanes. When a backplane driver is on, its output switches from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD to 2/3 VLCD. When a frontplane driver is on, its output switches from 0 V to VLCD, and when it is off, it switches from 2/3 VLCD to 1/3 VLCD. The LCD drive and timing section provides the multiplex signals and backplane driver input signals and formats the frontplane and backplane waveforms. The address pins are used to uniquely distinguish LCD driver from any other chips on the same bus and to define LCD driver as the "master" in the system. There must be one master in any system. The enable pin may be used as a third control line in the communication bus. It may be used to define the moment when the data is latched. If not used, then the data is latched after 128 bits of data have been received.
TIME FRAME VLCD BP1 2/3 (VLCD) 1/3 (VLCD) 0V VLCD BP2 2/3 (VLCD) 1/3 (VLCD) 0V VLCD BP3 2/3 (VLCD) 1/3 (VLCD) 0V VLCD BP4 2/3 (VLCD) 1/3 (VLCD) 0V
Figure 4. Backplane Sequence
MOTOROLA
MC14LC5003 * MC14LC5004 3-7
TIME FRAME VLCD BP1 0V FP DATA BITS 4321 0000 VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 1000 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 0100 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 1100 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 0010 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 1010 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 0110 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 1110 2/3 (VLCD) 1/3 (VLCD) 0V 1111 0111 1011 0011 1101 0101 1001 FP DATA BITS 4321 0001 BP1
TIME FRAME VLCD
0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V
Figure 5. Frontplane Combinations
MC14LC5003 * MC14LC5004 3-8
MOTOROLA
PIN DESCRIPTIONS
A0-A2 Address Inputs (Pins 42-44) The devices have to receive a correct address before they will accept data. Three address pins (A2, A1, A0) are used to define the states of the three programmable bits of MC14LC5003/MC14LC5004's 8-bit address. The address is 0111vwxy where v, w, x represent A2, A1, and A0 respectively. Where v, w, x=0, then A2, A1, and A0 should be tied to 0 V. Where v, w, x=1, then A2, A1, and A0 should be tied to VDD. The address pins must be tied to VDD. This defines the device as a master. NOTE
Note: In applications where the circuit will be isolated from external manual interference the system designer may take advantage of the self-programming feature. Upon power-on, address pins which are left open-circuit will be charged to VDD. However, care must be taken not to inadvertently discharge the pins after power-on since the address may then be lost. A similar feature is also available on the ENB pin. EXTERNAL RESISTOR VALUE 10 M
1M
100 k
10 k
1k
10 k
100 k
1M
10 M
OSCILLATOR FREQUENCY
Figure 6. Oscillator Frequency vs. Load Resistance (Approximate) FP1-FP32 Frontplane Drivers (Pins 36-27, 25-22, 19-15, 13-1) Frontplane driver outputs. BP1-BP4 Backplane Drivers (Pins 48-45) Backplane driver outputs. VLCD LCD Driver Supply (Pin 20) Power supply input for LCD drive outputs. May be used to supply a temperature-compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD. VDD Positive Power Supply (Pin 49) This pin supplies power to the main processor interface and logic portions of the device. The voltage range is 2.7 to 5.5 V with respect to the VSS pin. For optimum performance, VDD should be bypassed to VSS using a low inductance capacitor mounted very closely to these pins. Lead length on this capacitor should be minimized. VSS Ground (Pin 21) Common ground.
CAUTION
The configuration A0, A1, A2 = 000 should not be used. This does not give a valid address and is reserved for Motorola's use only. All three address pins should never be tied to 0 V simultaneously.
ENB Enable Input (Pin 41) If the ENB pin is tied to V DD, the MC14LC5003/ MC14LC5004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane drivers for display. If external control of this latching function is required, then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may be useful in a system where one MC145003/ MC145004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high. DCLK, Din Data Clock and Data Input (Pins 38, 39) Address input and data input controls. See Data Input Protocol sections for relevant option. OSC1, OSC2 Oscillator Pins (Pins 51, 50) To use the on-board oscillator, an external resistor should be connected between OSC1 and OSC2. Optionally, the OSC1 pin may be driven by an externally generated clock signal. A resistor of 680 k connected between OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving approximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 k gives about 100 kHz, which results in 100Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6.
DATA INPUT PROTOCOL
Two-wire communication bus DCLK, Din; three-wire communication bus DCLK, Din, ENB. MC14LC5003 -- SERIAL INTERFACE DEVICE (FIGURE 7) Before communication with an MC14LC5003 can begin, a start condition must be set up on the bus by the transmitter. To establish a start condition, the transmitter must pull the data line low while the clock line is high. The "idle" state for the clock line and data line is the high state. After the start condition has been established, an eight-bit address should be sent by the transmitter. If the address sent corresponds to the address of the MC14LC5003 then on each
MOTOROLA
MC14LC5003 * MC14LC5004 3-9
successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC14LC5003's internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5003, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC14LC5003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. MC14LC5004 -- IIC DEVICE (FIGURE 8) Before communication with an MC14LC5004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data line low while the clock line is high. After the start condition has been established, an eight-bit address should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the
controller reads from the LCD driver's 128-bit shift register on a first-in first-out basis. If the seven most significant address bits sent correspond to the address of the LCD driver then the addressed LCD driver responds by sending an "acknowledge" bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line Din low as an acknowledgment. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC14LC5004's internal counter latches the data to be displayed after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC14LC5004, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge-related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address.
MC14LC5003 * MC14LC5004 3-10
MOTOROLA
MOTOROLA
A2 FP1 FP2 A1 A0 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 129TH DCLK HIGH: (DOES NOT SHIFT DATA) 8-BITS ADDRESS 128-BITS DATA START ENABLE PULSE MAY OCCUR AS REQUIRED BUT MUST BE DURING DCLK HIGH.
D in
DCLK
START
ENB (IF USED)
Figure 7a. Data Input--MC14LC5003
Figure 7. MC14LC5003(SERIAL INTERFACE DEVICE)
BP Din x FP32 FP3 FP4 FP5 FP6 4 32 14 3 21432 14 32 14 3 21432 1 4321 FP1 FP2 x: 1(BPi, FPj) ON 0 (BPi, FPj) OFF
MC14LC5003 * MC14LC5004 3-11
Figure 7b. Serial 128 Bits Data
WRITE TO LCD DRIVER (LOW-ORDER BIT 02=0) LEFT HIGH BY CONTROLLER FP1 FP2 LEFT HIGH BY CONTROLLER
D in (FROM CONTROLLER) A2 A1 A0 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE
LAST DCLK PULSE (DOES NOT SHIFT DATA)
DCLK
MC14LC5003 * MC14LC5004 3-12
8-BITS ADDRESS 8-BITS DATA CONTINUES TO CLOCK DATA AND ACKNOWLEDGE PULLED LOW BY DRIVER PULLED LOW BY DRIVER (LOW-ORDER BIT=1) ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE 8-BITS ADDRESS 8-BITS DATA ADDRESS ACKNOWLEDGED BY DRIVER CONTINUES TO CLOCK DATA AND ACKNOWLEDGE LEFT HIGH BY DRIVER
START
D in (FROM LCD DRIVER) STOP ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH.
ENB (IF USED)
READ FROM LCD DRIVER
Figure 8 . Data Input MC14LC5004 (IIC Device)
D in (FROM CONTROLLER) LAST DCLK PULSE (DOES NOT SHIFT DATA)
DCLK
START
STOP
D in (FROM LCD DRIVER) LEFT HIGH BY DRIVER
MOTOROLA
MOTOROLA
LIQUID CRYSTAL DISPLAY FP1-FP32 FP1-FP32 BP1-BP4 FP30 FP31 FP32 680 k FP19 FP18 FP17 FP16 FP15 VLCD VSS FP14 FP13 FP12 FP11 DCLK FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 LCD DRIVER OSC1 OSC2 V DD BP1 BP2 BP3 BP4 A0 A1 A2 ENB FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 FP29 BP1-BP4 CONTROLLER
Din
Figure 9. Application Example
STROBE CLOCK DATA VDD VLCD VSS
MC14LC5003 * MC14LC5004 3-13
ON BUS
APPLICATION INFORMATION
Figure 10 shows an interface example. Example shows a semi-automatic SPI Mode (only start and stop conditions are done in non-SPI Mode). It contains the software to use HC11 with MC14LC5003 in manual SPI Mode.
VDD
1k
VDD
A0
A1
A2 OSC1
MOSI MC68HC11 SCK SS
Din DCLK ENB
MC14LC5003 OSC2
R = 470 k
BP1-BP4
FP1-FP32
1/4 MUX DISPLAY
Figure 10. Interface Example Between MC68HC11 and MC14LC5003
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0000 0000 0000 0000 0000 0000 0000 T T T T T T T ;=======CONSTANTS================================================= extram equ $A000 ;$A000 for 8K RAM stack equ $00FF ;last RAM byte intofs equ $1000 ;Internal Registers data equ $08 clock equ $10 enable equ $20 portd equ 8
A000 A000 A003 A005 A008 A00A A00D A010 A010 A014 A018 A01B A01D A020 A025 A026 A027 A029 A02D A030 A031 A033
T N M T M N T T U J T X T L H H R J T H M T
8E00FF 8638 B71009 C611 CEA05E BDA010
;=======PROGRAM BEGIN============================================= org extram ;Program into RAM cold lds #stack ;set stack pointer ldaa #$38 ;set of MOSI,SS,SCK staa $1009 ;DDRD ldab #17 ldx #send jsr spi end cold spi ldy bclr jsr ldaa staa brclr inx decb bne bset jsr rts ldaa staa #intofs portd,y #enable start 0,x $102A $29,y,#$80,*
18CE1000 181D0820 BDA031 A600 B7102A 181F2980FB 08 5A 26F2 181C0820 BDA04C 39 8633 B71028
again
;EN = 0 ;start condition ;SPI Mode Use ;SPDR ;next DATA
again portd,y #enable stop
;stop condition
start
#$33 $1028
;Normal Mode ;SPCR
MC14LC5003 * MC14LC5004 3-14
MOTOROLA
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
A036 A03A A03E A042 A046 A048 A04B A04C A04E A051 A055 A059 A05D A05E A05F A060 A061 A062 A063 A064 A065 A066 A067 A068 A069 A06A A06B A06C A06D A06E A06F
J J J J M T H M T J J J H T T T T T T T T T T T T T T T T T H
181C0808 181C0810 181D0808 181D0810 8673 B71028 39 8633 B71028 181D0808 181C0810 181C0808 39 7E F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 39
stop
bset bset bclr bclr ldaa staa rts ldaa staa bclr bset bset rts fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb rts
portd,y portd,y portd,y portd,y #$73 $1028
#data #clock #data #clock
;DATA = 1 ;CLK = 1 ;DATA = 0 ;CLK = 0 ;SPI Mode ;SPCR ;Normal Mode ;SPCR ;DATA = 0 ;CLK = 1 ;DATA = 0
#$33 $1028 portd,y #data portd,y #clock portd,y #data
send
$007E $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0
;LCD Driver Address ;Data to sent
;=======PROGRAM END===============================================
Example 1. Semi-Automatic SPI Method
Figure 11 shows another interface example. Example 2 contains the software to use HC05 with MC14LC5003 in serial data interface.
VDD
1k
VDD
A0
A1
A2 OSC1
DOUT MC68HC05 SCK
Din DCLK ENB
MC14LC5003 OSC2
R = 470 k
STROBE
BP1-BP4
FP1-FP32
1/4 MUX DISPLAY
Figure 11. Interface Example Between MC68HC05 and MC14LC5003
MOTOROLA
MC14LC5003 * MC14LC5004 3-15
PORTC DDRC SEN SCL SDA DOUT
EQU EQU EQU EQU EQU EQU ORG
$02 $06 $07 $06 $05 $FF $0050 1 1 $1FFE #$01 #$00
PORTC PORTDC ENABLE PIN, PC7 CLOCK PIN, PC6 DATA PIN, PC5 OUTPUT DATA
W1 COUNT
RMB RMB ORG FCB FCB
ADDRESS OF RESET VECTOR OF MC68HC805C4 RESET VECTOR
*** Main Program start at 0100 *** ORG LDA STA $0100 #DOUT DDRC
START
SET DATA LINE OUTPUT
AGAIN LDX BSET BSET READY BSET LDA STA BCLR CLC LDA STA LDA INCX BCLR ROLA BCC BSET JMP BCLR BSET DEC BNE DEC BNE BCLR BCLR BSET BSET BCLR RTS #$00 SDA,PORTC SCL,PORTC SEN,PORTC #$11 W1 SDA,PORTC IDLE STATE CLOCK AND DATA ARE HIGH EN=1 SET ADDRESS AND 8 CHARACTERS START CONDITION, DATA LOW WHILE CLOCK HIGH
LBYTE
#$08 COUNT SEND,X
8 BITS TO SHIFT GET A BYTE
LBIT
SCL,PORTC DZERO SDA,PORTC CLKHI SDA,PORTC SCL,PORTC COUNT LBIT W1 LBYTE SCL,PORTC SDA,PORTC SCL,PORTC SDA,PORTC SEN,PORTC
CLOCK LOW DATA BIT=0 ? NO, BIT=1 AND DATA HIGH DATA LOW CLOCK HIGH
DZERO CLKHI
LAST BYTE ?
STOP
STOP CONDITION DATA GOES HIGH WHILE CLOCK HIGH EN=0
*** End of Program *** *** LCD Address and Data *** SEND FCB FCB FCB RTS $7E $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF $FF, $FF, $FF, $FF, $FF, $FF, $FF, $FF LCD DRIVER ADDRESS DATA TO SENT
Example 2. Serial Data Interface Method
MC14LC5003 * MC14LC5004 3-16
MOTOROLA
PACKAGE DIMENSIONS
QFP FU SUFFIX CASE 848B-02 L
39 27
DS
0.20 (0.008) M H A-B S
-AL
-DB
DETAIL A
52 14
0.05 (0.002) A-B
V
0.20 (0.008) M C A-B S
DS
40
26
B
1 13
-DB
0.20 (0.008) M H A-B S 0.05 (0.002) A-B DS
B
-A,B,DDETAIL A
DS
V
0.20 (0.008) M C A-B S
F C E -H-CSEATING PLANE DATUM PLANE
M
DETAIL C J N
H
0.10 (0.004) G M D
0.02 (0.008) M C A-B S DS
BASE METAL
SECTION B-B
MILLIMETERS INCHES MIN MX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC -0.010 0.005 0.009 0.026 0.037 0.307 REF 5 0 10 7 0.005 0.007 0.005 0.012 0.510 0.530 0.005 0 ---
U
T
DATUM PLANE
-H-
R
Q
K W X DETAIL C
NOTES: 1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N Q R S T U V W X
MIN 9.90 9.90 2.10 0.22 2.00 0.22 -0.13 0.65 5 0.13 0 0.13 12.95 0.13 0 12.95 0.35
MAX 10.10 10.10 2.45 0.38 2.10 0.33 0.25 0.23 0.95 10 0.17 7 0.30 13.45 --13.45 0.45
0.65 BSC
7.80 REF
0.510 0.530 0.014 0.018 0.063 REF
1.6 REF
MOTOROLA
MC14LC5003 * MC14LC5004 3-17
BOND PAD LAYOUT
-X
+X
PIN 1
+Y
-Y
(c) HONG KONG I.C. DESIGN CENTER
Die size : 78 x 119 mil2 (1 mil ~ 25.4m)
BOND PAD COORDINATES
COORDINATES PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 PIN NAME X FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 NC FP19 FP18 FP17 FP16 FP15 VLCD VSS FP14 FP13 FP12 FP11 NC -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 -736.002 N/A -736.002 -588.802 -441.602 -294.402 -147.202 0.000 147.200 294.398 441.598 588.798 735.998 N/A Y 929.199 781.999 634.799 487.599 340.399 193.199 45.999 -101.201 -248.401 -395.601 -542.801 -690.001 -837.201 N/A -1205.601 -1205.601 -1205.601 -1205.601 -1205.601 -1205.600 -1205.600 -1205.601 -1205.601 -1205.601 -1205.601 N/A 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 FP10 FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 NC DCLK DIN NC ENB A2 A1 A0 BP4 BP3 BP2 BP1 VDD OSC2 OSC1 NC PIN NO. PIN NAME X 735.998 735.998 735.998 735.998 735.998 735.998 735.998 735.998 735.998 735.998 736.000 736.000 736.000 N/A 736.000 588.800 441.600 294.400 147.198 -0.002 -147.202 -294.402 -441.600 -588.800 -736.000 N/A Y -837.201 -690.001 -542.801 -395.601 -248.401 -101.201 45.999 193.199 340.399 487.599 634.800 782.000 929.200 N/A 1205.600 1205.600 1205.600 1205.600 1205.599 1205.599 1205.599 1205.599 1205.600 1205.600 1205.600 N/A COORDINATES
Dimemsions in m
MC14LC5003 * MC14LC5004 3-18
MOTOROLA

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